High speed serial

The output swing and offset depends on the bias current and termination resistance. LVDS typically uses 3. CML uses more current, and therefore this capacitance becomes less of a limiting factor to data throughput. A typical LVDS output stage requires four transistors to steer current into the load, usually using both P-channel and N-channel devices. A mixture of N- and P-channel makes it difficult to produce devices that have the same characteristics.

P-channel devices are often slower—that is, if an N-channel and a P-channel device are cascaded, the P-channel cannot pull up the signal as fast as the N-channel can pull down. This causes the output waveform to be distorted, which can lead to bit errors, and limits the speed at which LVDS can transfer data. Since CML only sinks current, it has true differential signal, which improves signal integrity. The eye diagram and bathtub curves of the LTC are shown in Figure 2. The eye diagram shows very little variation cycle to cycle of the CML logic output, and the bathtub curve shows that total jitter in the signal is less than 0.

This equates into a very clean uniform signal that can easily received by a properly terminated receiver. CML must be terminated for proper operation. OV DD must be between 1.

The signal has a common mode voltage of OV DD — 0. Xilinx provides a broad range of serial IP protocol support to accelerate design productivity:. The Xilinx Versal and UltraScale Architecture transceiver portfolio delivers exceptional value to customers in the following areas:. You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.

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